Design of Ternary Master-Slave D-Flip Flop using MOS-GNRFET

Graphene Nano Ribbon Field Effect Transistors (GNRFETs) are being investigated for a wide range of applications due to its unique characteristics like controllable threshold voltage, high I
_on
-I
_off
ratio, etc. One of the emerging areas of research on GNRFET is its utilization in beyond-binary logic and memory circuits designs. This paper presents new designs of a basic ternary D latch and a positive edge-triggered Master-Slave D flip-flop. The proposed designs exploit the electrical properties of GNRFETs and appears to be better than other similar designs in terms of delay, static power, and the average power. Simulations are done using a 16nm three ribbon MOS-GNRFET HSPICE model.