8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator

A 65nm XNOR-SRAM macro is presented for binary deep neural network (DNN) accelerator. It features 1) a custom XNOR-SRAM bit-cell design with 8 transistors (8T); 2) a fully parallel compute-in-memory capability of XNOR bit-counting for the inference. Multi-level sense amplifier is employed as Flash analog-to-digital converter (ADC) at edge of the array. The impact of ADC offset on the algorithm-level accuracy is statistically evaluated on a VGG-like XNOR-Net with the CIFAR-10 dataset, showing a marginal degradation ~1.77%. Read-disturb of SRAM bit-cell during parallel computation is also evaluated and its impact is minimized by lowering the word-line (WL) voltage. Silicon measurement results show that the proposed XNOR-SRAM unit-macro achieves a fast access time (2.3 ns) for parallel bit-counting and a high energy efficiency (44.8-62.8) TOPS/W depending on the WL voltage.