Design of Generic Floating Point Pipeline Based Arithmetic Operation for DSP Processor

In recent years, customer demand is for a DSP processor with high and efficient performance. To meet this demand, the hardware is needed which can process the highspeed signal and perform arithmetic floating point operations. Earlier, the majority of algorithms which were implemented onto FPGA were of the fixed point. With the present developments, implementation of floating points on FPGA is becoming a trend because FPGA takes less time for development and less cost compared to ASIC design. The floating point units design needs very high accuracy. In this paper, designing of single precision and double precision floating point arithmetic operations are done and implemented on FPGA for signal processing with the MAC unit using Verilog language. The codes are written in Verilog. The main objective is to compare the area and timing between single and double precision of floating point unit (FPU) and MAC unit. The proposed design is simulated and implemented on Spartan 6 FPGA.