Power System Emulator Based on PLL Architecture

For an extensive power system network, solving the power-flow problem becomes computationally very burdensome. Current numerical simulators use the iterative approach to find the optimal power-flow state in the power grid, which are prone to numerical instability, convergence issues. Moreover, the existing numerical optimizers are slow, depending on the size and the complexity of the power systems. For massive power grids, large memory consumption and calculation steps are required to find the solution which puts more constraint on the available resources for the processor-based digital solvers. In this paper, a feasibility study of a different methodology is presented, where an alternative analog/mixed-signal circuitry has been introduced to build a custom computer. The proposed accelerator provides the power-flow solution by emulating the actual power system grid inside a miniature VLSI chip. This article demonstrates the feasibility of using a Phase Locked-loop (PLL) based architecture to implement an emulator for a 14-bus system, which reaches to the steady-state condition after 15 μs, exhibiting three orders of magnitude computational speed improvement.