Performance Analysis of Sub-10nm Vertically Stacked Gate-All-Around FETs

Gate-All-Around Nanosheet Field Effect Transistor (GAA-NSFETs) have emerged as the solution to avoid short channel effects (SCEs) at the 10-nm technology node and beyond. In this paper, we have investigated vertically stacked NSFETs from electrical aspects as the degradation in drive current is a significant concern for GAA-NSFETs. We evaluate the impacts of geometrical variations, doping concentration, height and width of the nanosheet on the performance of triplechannel vertically-stacked NSFETs. Each design parameter has been analyzed through various figure-of-merits (FOMs) such as the threshold voltage (V
_TH
), on-state current (I
_ON
), off-state current (I
_OFF
), subthreshold slope (SS) and drain induced barrier lowering (DIBL). Finally, the enhancement in current drivability can be possible by minimizing the NS doping concentration and increasing both the nanosheet height and width.