Chronos Link: A QDI Interconnect for Modern SoCs

In the last decade, SoC designs saw dramatic changes in their specifications. While the main drives kept being increasing performance for lower area and power, the design challenges shifted towards moving data across the die. This is due to different factors, among which we highlight the growth in SoC complexity and the growth of Machine Learning (ML) applications. The former has to do with the mobile era, where SoCs such as Exynos
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or Snapdragon
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[1] are developed as generic platforms for a variety of applications, such as smartphones and virtual reality devices. These SoCs integrate hundreds of IPs, such as microprocessors, DSP units, memories and GPUs. The growth in the number of IP blocks means more interconnects are required to allow communication among them, increasing the adoption of NoC solutions, such as those provided by Netspeed or Arteris [2].