A Low-Noise, Low-Power, Dynamic Latched Comparator Using Cascoded Structure

In this paper, a design for a low-noise, low-power, dual-tail dynamic latched comparator is introduced. The input referred noise is reduced through the use of a larger gain comparator dynamic amplifier; a cascode structure is adopted for such an amplifier with a direct effect on the power. To fix this problem without degrading the gain or the input referred noise, bulktuning is applied to the amplifier bias transistor. In addition, a nonconventional power-efficient latch structure is used. Designed in a 130nm UMC process, with a supply voltage of 1.2V and at a clock frequency of 1-GHz, the proposed comparator has an input-referred noise of 290μV, and an input offset voltage of 4.1mV while consuming 100μW of power with a power efficiency of 100fJ/conv. The maximum achievable frequency is 1.25GHz for a differential input 292μ V.