Delay and Power Efficient FIR Architecture for Noise Suppression of EOG Signal

In this paper, we proposed a modified FIR filter using Canonical signed digit (CSD) technique for de-noising the Electro-Oculography (EOG) signal. A dipole was formed between cornea and retina in an eye, resulting in voltage difference with occurrence of eye movement, which in turn generates an electrical signal. These signals are called as EOG and are useful in many medical and bioelectrical applications. To remove the noise in EOG signal an enhanced 16-bit FIR filter was used. The proposed FIR architecture uses CSD based multipliers, unlike the conventional shift-add the proposed architecture provide greater improvement in power and delay. CSD is used in order to reduce the design complexity of the multiplication by representing the filter coefficients in CSD format. The proposed approach was implemented on Xilinx FPGA development kit. By comparing the synthesis results for existing and proposed methods, which has achieved an improvement of 12.60% and 11.76% in Power Delay Product (PDP) and Area Delay Product (ADP) respectively.