Optimization of PLL Loop Filter Control to Reduce Time Delay Using Genetic Algorithm on Single Phase Grid Tie Inverter Application

Tuning the internal parameters of the phase locked loop (PLL) correctly is a problem that must be solved in order to successfully lock the reference signal from the dynamic grid because of the large load that suddenly changes. In this paper, tuning methods based on genetic algorithm (GA) will be presented. Four performance test indicators, i.e. integral squared-error (ISE), integral absolute-error (IAE), integral time-weighted absolute-error (ITAE), and integral time-weighted squared-error (ITSE) will be used in the GA training algorithm. The objective functions used are minimum error and settling time. Comparison results using computer modeling of the four performance test indicators shown that the application of ITSE on GA optimization gives the parameters with the best influence on PLL performance under sudden change in the load on the grid. The PI-GA-ITSE error is 17-28% smaller than PI-GA-ISE, 13-26% smaller than PI-GA-IAE, and 41-56% smaller than PI-GA-ITAE.