Improving the Partial Product Tree Compression on Signed Radix-2m Parallel Multipliers

Arithmetic operations are intrinsic to any embedded devices, and they usually have a significant impact on the circuit speed, area, and power consumption. Applications like video processing, digital signal processing, machine learning, among others, rely heavily on multipliers to execute their algorithms. Radix-2
^m
multipliers have been reported as one of the most power-efficient circuits. However, their architecture has not been explored nor optimized to improve the circuit quality. This work proposed two sign extension optimization techniques for these multipliers, aiming for better power efficiency and a smaller area. The baseline radix-4 (m=2) multiplier and its optimized versions were synthesized in a commercial 65nm technology to evaluate their performance. Results show that the optimized versions achieve power efficiency gains from 16.4% up to 78.6%, with circuit area reduction up to 49.2%.