Fan-Out RDL-first Panel-Level Packaging for Heterogeneous Integration

In this study, the fan-out chip-last panel-level packaging for heterogeneous integrations is investigated. Emphasis is placed on the design, materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10mm × 10mm) and two small chips (7mm × 5mm) by a fan-out method with a redistribution-layer (RDL)-first substrate fabricated on a 515mm × 510mm panel. Reliability assessments such as the thermal cycling of the heterogeneous integration of the 3-chip package printed circuit board (PCB) assembly are performed by a nonlinear temperature- and time-dependent finite element simulation.