Trench Isolation Technology for Cost-effective Wafer-level 3D Integration with One-step TSV

A new trench isolation technology is proposed for one-step TSV integration scheme. Si trench etching and SiO
₂
filling process are developed for electrical isolation of one-step TSV and metal contamination free process. Process challenges are overcome by design/process concurrent optimization. Four different types of trench isolation layouts are proposed for both of signals and power/ground TSV, Trench design as well as gap filling process are optimized for each type of trench isolation to achieve complete coverage of trench top. The position of air gap top is important, because opening might be created during subsequent CMP step. This trench isolation technology is an enabler of metal contamination free one-step TSV process. In addition, the trench isolation could enable around 75% reduction of TSV capacitance compared to conventional TSV sidewall isolation, which contributes high-speed data transfer and low power consumption.