3D Micro Bump Interface Enabling Top Die Interconnect to True Circuit Through Silicon Via Wafer

During last couple years, the market of IC package successful to implement Cu pillar Bump as a mainstream of high density flip chip packaging solution in each of product application market. High performance computing product requires advanced Si node, large die and multiple die side by side floor plan on large FCBGA. However, large scale die dimension and substrate form factor to brings up expensive wafer mask fabrication, substrate fee, complex backend assembly process control and specific bill of material to maintain better mechanical performance. In other words, there is a significant help from package assembly since Moore Law is slowing down. After reviewed the package evolution trend of 2.5D package, Cu pillar bump owns better electron migration performance which is suitable for high power and low latency product application. 3D package with μBump architecture has three kinds of advantages. First, die partition to shrink die area and enhance wafer yield; Second, reduce signal latency & insertion loss compared to 2.5D since applying 50um TSV wafer thick. to reduce signal transmission path; Third, high power IC which used advanced Si node and put on top position of 3D stacking to contact thermal interface material and heat sink directly to realize better system thermal dissipation requirement.In order to well define optimum construction while utilizing less than 30um μBump pitch 3D package vehicle rely on mechanical simulation trend to find out critical dimension on μBump of top die and TSV wafer structure design. The paper will compare die to die signal connection architecture such as 2.5D, FO-MCM and FO-EB packages. Uses a series of fundamental studies to define μBump stack up composition and protection material in terms of 3DIC platform baseline establishment. Based on dominated key factors of stress simulation and actual verification result to find out bump joint methodology. First of all, chip module of 3D TV (Test Vehicle) samples is stacked with top die and bottom die by the joint of μBump and μPad. μBump has three structures: CS (Cu + Solder), CNS (Cu + Ni + Solder), and CNCS (Cu + Ni + Cu + Solder). Moreover, the validation flow is proposed. In the first phase, the metallic reaction test of 1
^st
3D TV samples and stress simulation of μBump are performed. In the second phase, based on the results of the first phase, to modify the dimension and materials of μBump and μPad, and to build the 2
^nd
3D TV samples for reflow test then obtain the best combination of structure and dimension for μBump by multiple reflow test.In conclusion, this study successfully completed pathfinding activity of 3D package with the joint of μBump (less than 15/30, μm) and μPad, and found the best structure and dimension for μBump and μPad.