Graphene Nano-wire TFET with Extremely Low SS

In this paper, intrinsic channel graphene-based extremely low SS nano-wire is proposed. In this proposed nanowire TFET hetero-dielectric gate is used which leads to the reduction of SS below 60 mV/dec. A comparative analysis of Silicon nano-wire and Graphene nano-wire is also performed. In case of silicon nanowire, I
_ON
/I
_OFF
ratio is in the range of 10
¹²
with low ambipolarity and SS (45mv/decade) but in graphene nanowire very low SS is observed up to 3 mV/dec. The ambipolarity in graphene nano-wire is comparatively high but by the using hetero-dielectric gate & large bandgap material at the drain region, ambipolarity of graphene nano-wire is reduced up to the great extent. The proposed device structure has been simulated on santauras TCAD device simulator & the results are compared with that of the conventional TFET.