Limits on Hysteresis-Free Sub-60 mV/Decade Operation of MFIS Nanowire Transistor

In this work, we present purely device-dependent conditions for achieving hysteresis-free sub-60 mV/decade (HF-sub-60) current transition in metal-ferroelectric-insulator-semiconductor (MFIS) nanowire transistor. The proposed bias-independent conditions for HF-sub-60 operation are also verified through conventional bias-dependent capacitance matching. Optimal ranges of ${T} _{\text {fe}}$ for achieving HF-sub-60 current transition are examined for 1) varying radii of nanowire; 2) three ferroelectric materials (Al-HfO2, hafnium zirconium oxide (HZO) and Y-HfO2); 3) nanowire and planar architectures; and 4) coercive field and remnant polarization variations. Furthermore, the impact of gate length scaling is incorporated into the developed model. The proposed methodology in this article provides new and detailed guidelines into the selection of device and process parameters, ferroelectric materials, and device topologies for facilitating high internal voltage amplification factor, improved subthreshold swing and hysteresis-free operation in MFIS transistors.