A Quadrature Sub-Sampling Phase Detector for Fast-Relocked Sub-Sampling PLL Under External Interference

Conventional sub-sampling PLLs suffer from unstable problems under external interference due to potential long relock time in some cases. To solve this issue, a novel quadrature sub-sampling phase detector (QSSPD) is proposed in this brief to eliminate phase error ambiguity and compensate gain non-linearity. Hence, relock time under external interference is dramatically reduced while maintaining the low in-band noise characteristics simultaneously. Moreover, a study on the dynamics of sub-sampling PLL is carried out based on dynamic equations of the sub-sampling loop. A 2.3-2.5 GHz integer-N SSPLL has been prototyped in a 65nm CMOS process to show the superiority of the proposed QSSPD, which reduces the relock time from 16.3μs to 4.8μs and even 1.1μs compared to conventional SSPD while suffering 5.4MHz frequency interference.