Methodology for Detecting Glitch on Clock, Reset and CDC path

In this paper, an attempt has been made to propose a methodology for detecting glitch on clock tree, reset trees, and clock domain crossing (CDC) paths. These glitches, if not verified appropriately, will cause chip re-spins when detected late in the design cycle. Modern designs contain multiple IPs from different sources, and when they are integrated, glitch prone logic can be introduced unintentionally. At the same time, CDC paths with multiplexers or combinational logic are prone to glitch defects being introduced by synthesis. These glitches may be captured by a register when crossing clock domains, causing a functional failure. So, it becomes essential to catch glitch issues in the design in an early phase of the design cycle.