A 0.3-V to 1.8–3.3-V Leakage-Biased Synchronous Level Converter for ULP SoCs

This letter proposes a robust synchronous wide-range clocked level converter (LC) that converts subthreshold input signals to high I/O voltages for ultra-low power (ULP) SoCs. By biasing the circuit using nMOS leakage current, the design offers robust operation across a wide range of lowand high-supply voltages as well as PVT variations. The design was fabricated in 55-nm CMOS process and shows 60.5-fJ (VDDH = 2.5 V) switching energy, marking a 2.6× improvement over prior works.