Study on Etch Slope in Fin and Source/Drain Etch Process of Vertically-Stacked Nanosheet Gate-All-Around MOSFET

The electrical behavior of vertically- stacked nanosheet (NS) gate-all-around MOSFET (GAAFET) having slanted NS channel and source/drain resulted from the etch profile in reactive ion etching processes was investigated through TCAD device simulation. It was observed that the off current (I
OFF
) and threshold voltage (V
TH
) were variable depending on the etch slope (E/S) and the number of stack (n stack).