A New Implementation Approach for Reliability Design Rules against Plasma Induced Charging Damage from Well Configurations of Complex ICs

Plasma induced charging damage of MOS transistors originating from well charging (triple well or deep n-well configuration) is investigated for two different technologies. It is shown that the degradation on MOS transistors can impact the reliability of a product in comparison to earlier published data where a yield loss characteristic was reported on the basis of initially high MOS gate oxide leakage currents. For the first time a drift in MOS threshold voltage was recorded associated with well charging. Experimental data from this work and earlier published well charging results describe the same failure mechanism, but degradation characteristics are different, hence indicating the relevance of appropriate reliability investigations to ensure a robust product design according to the design for reliability strategy. It is demonstrated that a reliability stress on adequate product-relevant test structures is required for a necessary well charging assessment.A suitable protection method against well charging is described and implemented into a newly formulated well charging design rule which is practicable enough for implementation in electronic design automation tools. However a design rule checker for well charging requires a different concept than one for commonly known plasma induced charging on MOS gate electrodes.