Turn-on Gate Resistor Optimization For Paralleled SiC MOSFETs

Parallel connection of MOSFETs is often used to increase the current handling capability of power modules. However, the difference of parasitic parameters and switching characteristics of the paralleled devices may lead to current unbalance and oscillation that limits the overall performance. This paper developed an analytical model for the transient current sharing and inherent oscillation for two paralleled SiC MOSFETs’ turn-on process. Based on the developed model, the influences of parasitic parameters are investigated. Optimized gate resistor selection to compensate circuit mismatches is discussed. Spice-based simulation and experiments are conducted to verify the analysis.