Optimization of Floorplan Strategies to Reduce Timing Violation on 28nm ASIC and Scopes of Improvement for Data Center ASICs

Electronics industry is moving towards rapid technology growth in which ASIC designing is the prime contributor. The data centers and various electronics systems are shrinking hence the need is to have the gadget as tiny as possible and also to have power as low as possible with high performance. With the advent of lower technology nodes, the entire electronics world is getting on a single chip making System on Chip (SoC). The miniaturization in channel length yielding smaller transistor and the high dense chip has increased challenges of engineers day by day. Also increasing demand for high-frequency design is a big challenge for the ASIC engineers. In this paper, the backend flow- PnR flow is analysed with various constraints and demonstrated with different physical design techniques to optimize the timing without compromising on the design features. Setup timing optimization is a very important and critical step of the backend design of SoCs. Many techniques are available to guide the designer to close the design timing. The conventional implementation of PnR flow has been started and applied different method to reduce the timing violations and show that the design is routable with minimal DRCs.