An External Capacitorless Low-Dropout Regulator With 5.58uV Integrated Output Noise From 10 Hz to 100kHz Using Adaptive Bias Technique

Herein an ultra-low-noise capacitor-less low-dropout regulator (CL-LDO) is presented for noise-sensitive circuits. By using adaptive bias technique and an adaptive left-half plane zero compensation circuit, the stability of the proposed CL-LDO can be well retained from 100 uA to 100 mA of load current(I
L
), and the quiescent current can be reduced to 68uA. An optimized folded cascode error amplifier with high frequency feedforward capacitors is used to achieve ultra-low-noise and higher product of gain and bandwidth (GBW). These techniques allow the CL-LDO to reach a GBW of 70 MHz and a 5.58 uV integrated output noise from 10 Hz to 100 kHz at heavy load (I
L
= 100 mA). The CL-LDO was designed in a 180-nm CMOS process, its power supply rejection ratio (PSRR) is less than -69 dB at the frequency below 1 MHz, and occupies an area of 0.042 mm
²
.