High Speed MLSD Equalization for Serial Link

In this paper, the digital part of maximum likelihood sequence detection (MLSD) equalization is presented for serial links. In order to shorten the critical path delay of independent forward sliding block with the ACS recursive structure, the metamorphosis partial full adder (MPFA) is used to construct the ACS with parallel execution of “add” and “compare”. 3 ways parallel independent forward sliding block with ACS recursive structure is synthesized by TSMC 0.18$\mu$m CMOS technology. The results show that the maximum throughput is 1.27 Gb/s under a clock frequency of 0.211 GHz, and the consumption of logic units is 729K