Metrology and Inspection: Challenges and Solutions for Emerging Technology Nodes

Multiple, simultaneous trends emerging in semiconductor device technology pose challenges both in engineering manufacturable processes and with developing efficient, fast metrology and inspection solutions with improved sensitivity for process control. For instance, both memory and logic use 3D structures now-manufacturers no longer deal with simple planar structures but must monitor sidewall thickness, conformality, and repeatability of deposition and etch processes to engineer complex shape profiles, deep trenches, and contact holes with excellent uniformity. Material complexity also continues to increase significantly; for example, the metal gates of today can consist of up to 6 or more layers (most of which are only a few nm thick), compared to a single layer of thick polysilicon several nodes back. In addition, the process and metrology budgets for most processes continue to shrink along with particle and defect sizes of relevance. All these factors result in increased metrology techniques used to monitor IC manufacturing today. This paper presents an overview of these techniques, covering some of the challenges and solutions in metrology and inspection for emerging technology nodes.