An Automated Tool for Design Space Exploration of Matrix Vector Multiplication (MVM) Kernels Using OpenCL Based Implementation on FPGAs

OpenCL is a High-Level Synthesis (HLS) based framework that relaxes the programmers considering design time and design complexity. A single OpenCL kernel can be designed in numerous ways by tuning the design knobs. For a given setting of design knobs, logic synthesis of each OpenCL- based design can take several hours. Therefore, the Design Space Exploration (DSE) to search for an optimized design is prohibitive. This paper presents an automated CODE tool to implement an OpenCL-based Matrix-Vector Multiplication (MVM) kernel optimized for throughput and area.