Circuit Level Design Methods to Mitigate Soft Errors

The mitigation of soft errors should be considered in all design abstraction levels, from a high level to the physical one. This tutorial is focused on the circuit and physical design levels. Transistor reordering or transistor arrangements is an important way to improve robustness. The placement of serial transistors as far as possible to the cell output improves at least 4.9% the robustness of logic cells to the power variability, reaching 7% for the AOI21 cell. Another issue is the SET response under process variability using different transistor topologies. For all logic functions analyzed, regardless of the adopted topology, the LETth considering the WFF impact is smaller than the LETth at ideal conditions. Circuit-Level hardening techniques are used to mitigate Soft Errors. For the near-threshold regime, the close topology is less sensitive than far topology for all levels of LET investigated. However, the gains of this technique are more significant for lower LETs. The same tendency was verified when decoupling cells were connected in a NAND2 output. The soft error mitigation can reach around 37% and 24.5% for a LET equal to 20MeV.cm
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. mg
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when the AOI21 gate adopts the close topology, and the NAND2 adds the decoupling cells in the output, respectively. Another technique explored is the use of sleep transistors. It is also done an evaluation of variability when using Schmitt Trigger on full adders' layouts.