Design of a Low Power Processor for Embedded System Applications

A low power processor for embedded systems is designed and implemented. The proposed processor can operate on RV32E instruction set architecture using a modified MIPS micro-architecture. Clock gating technique and Standby mode are applied to reduce power consumption. The design is first entered and simulated at RTL using Verilog® to check its functionality, then translated, mapped, and optimized into a 180 nm CMOS technology using cell design library. The resulting layout of the processor is validated against the design at RTL to prove its correctness. The total area of the layout is about 285 μm by 285 μm, which is equivalent to about 7800 gates. For performance, the proposed processor can operate at a maximum clock frequency of 32 MHz, with an average current consumption of 189 μA in normal mode and 11.1 μA in standby state for a supply of 1.8V, or about 5.68 μW/MHz. In comparison with previous work, our proposed processor consumes much less power significantly.