Design and Test of a SRF-PLL Based Algorithm for Positive-Sequence Synchrophasor Measurements

This paper presents the design, analysis and experimental testing of a SRF-PLL based algorithm for positive-sequence synchrophasor measurements in compliance with the IEEE C37.118.1-2011 and C37.118.1a-2014 standards. The proposed approach consists of a three-stage algorithm, being the first one a three-phase demodulation, which detach the positive-sequence from the negative sequence signal in the frequency domain, as well as removes the zero sequence. The second stage is a finite impulse response filter (FIR) that is applied in order to improve the noise and interference rejection. Such class of digital filters was chosen by its characteristics of linear phase and constant group delay. Finally, the last stage is carried out by a synchronous reference frame phase-locked loop featuring magnitude normalization and proportional-integral controller, which estimates amplitude, phase, frequency and rate of change of frequency. The experimental results obtained by a test platform show that steady-state criteria are met.