First measurements on a discrete-time front-end in 28-nm CMOS technology for timing pixel detectors

This work presents the first results on a CMOS analog front-end in 28 nm commercial technology. The proposed scheme was designed to be compatible with future 4D vertex detector requirements for high energy physics experiments, such as: high granularity with a pixel pitch smaller than 100 μm, an average event-rate per unit area of 3 GHzcm
^-2
[5] and a radiation dose up to 10
¹⁴
MeV n
_eq
cm
²
. In order to fulfill these system requirements the front-end needs to integrate time measurement capabilities at the pixel level with a resolution better than 100 ps and a power consumption of the order of 10 μW per channel. Analog solutions has been adopted to minimize the effect of per-channel mismatch and process variation on the timing measure with minimal external control. A front-end with an auto zeroed comparator was chosen for this purpose due to its ease of control and low power consumption. A first prototype ASIC has been manufactured and is now under test. In this paper first measurements on its timing performance and offset-compensation capabilities are presented.