Low-Cost LWIR-Band CMOS Infrared (CIR) Microbolometers for High Volume Applications

This paper provides an overview of the studies and the current status for the development of a novel, low-cost, and CMOS foundry compatible approach for implementing microbolometers with standard CMOS and simple post-CMOS subtractive MEMS processes. This CMOS infrared detector technology is shortly called as the CMOS IR (CIR) technology, and it can be used to implement Focal Plane Arrays (FPAs) for infrared imaging in the LWIR-band ( 8-12 μm wavelength). Post-CMOS processes require only one mask lithography process and simple subtractive etching steps to obtain suspended bulk micromachined microbolometer pixels, where the detector element can be formed with standard CMOS layers and devices such as n-well layers, diodes, polysilicon, and some other CMOS layers and devices. Sensors of various pitch sizes (such as 70μm, 60μm, 50μm, and 35μm) and various FPA formats (such as 160×120, 80×80, and 40×40) have been demonstrated; some of these studies resulted in real commercial products in a VC funded spin-off company. The recent commercial products have a 35μm pixel pitch implemented using a 0.18μm CMOS process. One of these is a 80×80 microbolometer FPA has a die size of 5.4mmx6.5 mm and dissipates 20mW; the fabricated sensor is measured to provide NETD values of 163 mK at 17 fps and 71 mK at 4 fps with f/1.0 optics in a dewar, while using only the standard CMOS layers. When this FPA is wafer level vacuum packaged with a silicon cap wafer with one side AR coating, it provides a 112 mK NETD at 4 fps with f/1.1 optics. Another commercial product is the 160×120 FPA, which has a die size of 9.3 mm x 9.1 mm and dissipates less than 50 mW at 30 fps while operating with a 3.3V suppy. The sensor is measured to provide peak NETD values of 161 mK, 117 mK, and 90 mK at 17 fps, 11 fps, and 4 fps, respectively, in a dewar with f/1.0 optics. These performances are more than enough for a number high volume low-cost consumer market applications like advanced presence detection, human counting, smart offices/homes/cities, and other IoT applications. The performances can be improved further by using finer pitch standard CMOS processes as the CIR approach is scalable, allowing to reduce the pixel pitch even further while increasing the array size and/or improving the sensor performance if necessary for automotive, smart phone, and various other low-cost, high volume markets.