Delay Matrix Based Timing-driven Placement for Reconfigurable Systems-On-Chip

Reconfigurable system-on-chip (RSoC) is a device that contains configurable logic blocks and hard IP cores in the single chip. Designing high-speed digital circuits in RSoC requires efficient timing-driven placement algorithms. In this article we present a new timing-driven placement algorithm based on simulated annealing method for island-style reconfigurable system-on-chip. We developed a novel cost function based on half-perimeter wire length and a new delay model. Lookup matrices for both global and local interconnections are used to accurately predict the delays given the placement of nets' terminals. The proposed algorithm is implemented and tested using ISCAS-85 and ISCAS-89 benchmark suites. Experimental results show that the proposed algorithm in comparison with wirelength-driven version is able to reduce the delays and therefore improve the circuit performance in RSoC.