The Simulated Annealing Based Logical Resynthesis Method for LUT-based FPGAs

The paper proposes the simulated annealing based method of logical resynthesis for LUT-based FPGAs. For this method special graph model and transition logical operators on this graph were developed. To solve the resynthesis problem simulated annealing algorithm is used. It is applied over small subgraphs of the original circuit within an iterative cycle. While annealing procedure the developed logical operators change the structure of the graph without changing its logical function. The objective function for the area optimization of the circuit by reducing number of graph nodes was developed. The considered method was tested on the set of the combinational circuits from the ISCAS-85 benchmark. The test results show the maximum area reduction up to 34% and 16% of an average area reduction compared to circuits obtained by FlowMap algorithm.