Design of a Low Power PLL in 90nm CMOS Technology

A PLL is a key element in clock generation and wireless transceivers. This paper presents the design of fast locking PLL. The PLL is designed in Virtuoso tool by Cadence in Analog Design Environment using GPDK 90nm CMOS technology with operating frequency of 1GHz and lock time of 100ns. A current starved VCO is exploited to bring down power consumed and achieve high frequency. Various simulations were performed using Spectre simulator. The PLL consumes total power of 4.2mW at supply voltage of 1.8V.