An Optimized FPGA Implementation of DCT Architecture for Image and Video Processing Applications

The development of portable devices such as digital cameras and mobile phones led to higher amount of research being dedicated to image and video processing systems. In particular, video processing coding technique such as High Efficiency Video Coding (HEVC) requires low power consumption for the multimedia applications, this leads to extensive development in low area and high speed algorithms. The log time Discrete Cosine Transform (DCT) is increasingly employed for compression standards, since it has remarkable energy compaction properties. Pipelined and MAC based DCT have been implemented in digital hardware to offer better compression at very low circuit complexity. In this paper, a Time division multiplexing (TDM) based DCT architecture is implemented using the concept of resource sharing principle which possess low computational complexity and high speed. This hardware implementation results in reduced area and increased speed compared to the conventional DCT architectures implemented in Field Programmable Gate Array (FPGA) devices.