An optimal hardware implementation of the KECCAK hash function on virtex-5 FPGA

Security has become a very demanding parameter in today’s world of speed communication, one of the methods to ensure information integrity is the use of hash function which generates a stream of bytes (hash) which must be unique. The Keccak hash function is one of more than fifty candidates accepted by NIST for the SHA-3 hash function competition. In this article, an optimal implementation of this function will be presented. This implementation intended to reducing circuit complexity, and increasing performance hardware implementations of this cryptographic hash function. The proposed design is coded in VHDL and implemented on Virtex 5 FPGA.