Assembly Courtyard Improvement Using Silicon Capacitors: New Approaches for Signal and Power Integrity

Today's electronic circuits dedicated to high-frequency usage, low inductive parasitics or well-matched signal lines require smaller and smaller passive components. Especially for capacitors, the current trend in size reduction comes along with a struggle in assembly to keep good balance between performances and packaging rules. Hence, the area ratio between a capacitor's real area and the same capacitor's assembly courtyards goes bigger. This is particularly true for ceramic components in which you need to consider the land pattern but also the keepout between two different components' land patterns. The biggest disadvantage of large courtyards is for boards where several capacitors are placed very close to each other, usually in parallel, for applications such as decoupling for process units or DC-blocking/AC-coupling capacitors along signal lines in optical networking. Silicon capacitors can overrule some of the current limitations experienced by designers in those domains. Firstly, an analysis of real courtyard will be done on two capacitive technologies suitable for small packages, to show the real state-of-the-art in courtyard for small components. Secondly, we will propose some PCB design and architecture improvements in various conditions, using silicon capacitors.