A Reconfigurable Cache Structure Design for Multi-core SOC

Cache is a common method for mitigating the difference in data bandwidth between chip and external memory. This paper proposes a shared storage structure for a heterogeneous multi-core SOC system face to high-density calculation. The storage architecture uses a reconfigurable design approach which uses a part of the secondary shared cache as a local private store of the FFT compute node. This structure takes into account resource consumption and computational efficiency, and can save a large amount of on-chip storage resources compared to the common secondary shared cache. Compared with the cache-free structure, this structure can provide up to 41.1% acceleration ratio.