A Low-Cost and High-Throughput Virtual-Channel Router with Arbitration Optimization

Network-on-chip (NoC) has emerged as an on-chip interconnect technology that overcomes the constraints of traditional bus-based system. Virtual-channel router with transmission priority plays an important role especially in many-core chip multiprocessors (CMP) executing different applications. In this paper, we propose two arbitration optimization methods based on virtual-channel router, consisting of scoring crossbar arbitration and arbitration interception. The design has been implemented on the Xilinx ZCU102 FPGA board, and the results show that our work outperforms the traditional virtual-channel router in the NoC while reducing logic resource by approximately 10
^%
and achieving 2x better performance.