Study of Suppressed Carrier Scattering Effects and Carrier Quantization in Tri-Gate FinFET for SoC Applications

In this paper, the carrier Quantization effects and carrier scattering has been described in accordance with the leading 22nm technology for the multiple gate device. Also, the various short channel effects and their impacts on the device parameters. The subthreshold swing and DIBL was found to be within the acceptable limits and thus the variation in the threshold voltage with respect to the drain voltage and its impact on the device on-state current has been studied. The device may also be used for ultra-low power, high performance and high-density System on Chip (SoC) Applications and will be an ideal option when it's come to improved electrostatic control as compared to the existing technology as Steep Retrograded Doping Profile has been used in the device. The device was simulated using the Sentaurus TCAD and the mathematical operations have been out using MATLAB and Origin Pro.