High Performance Low Cost Package and Platform Design for 56G PAM4 SerDes

This paper will walk-through the process and challenges of design and integration of 56G PAM4 PHY into a low cost SoC package and platform targeting 5G base stations market. In order to deliver best in class design and meet strict electrical compliance from both the SerDes designer and the IEEE802.3 standards, an amalgamation of signal integrity optimization techniques are addressed in this paper.