Analytical Model Developed for Precise Stress Estimation of Device Channel Within Advanced Planar MOSFET Architectures

An analytical model for the precise stress estimation of device channels is developed and demonstrated in this article. The resultant stress magnitude under considered stress resources, including strained source/drain (S/D) and intrinsic stressed shallow trench isolation (STI), is carefully predicted and compared. The calculated accuracy of the presented model is validated through finite element simulation by a given example of the Si/SiGe material system arranged in S/D local regions and surrounded in the STI field. The rapid prognosis ability of the proposed model is performed on Si, Ge, and group III-V channels of nano-scaled transistors under specifically designed stressors. The S/D dependence of performance variety for all considered device materials can be directly estimated by changing the designed S/D length substituted into the analytical model. Moreover, the variations in induced mobility gain are further quantified using stress-piezoresistance relation. The analytic results indicate that the strained Ge pMOSFET outperforms other strained devices, such as Si and In0.53Ga0.47As channel materials, while identically designed strained level resulting from the lattice mismatch of S/D stressors is considered. Furthermore, the unstrained GaAs-based nMOSFET integrated with lattice-matched S/D Ge, indicating its superior electron mobility as compared with the S/D strained Si and Ge nMOSFETs owing to its advanced initial mobility. Accordingly, the systematically analytic flow of stress-induced device performance prediction is demonstrated via the present analytical solution integrated with corresponding piezoresistance models.