Programmable Auxiliary Co-Processing Unit for H.264 Decoder

This paper implements a hardware accelerator for H.264 video decoder by interfacing it as an Auxiliary Processing Unit (APU) with the embedded PowerPC (PPC440) processor on Xilinx Virtex-5 FPGA. The H.264 APU accelerator is tested with various video sequences and found 7× acceleration as compared to its equivalent software realization in the PowerPC embedded processor.