An Ultra-Low On-Resistance Triple RESURF Tri-Gate LDMOS Power Device

An ultra-low on-resistance triple RESURF LDMOS power device with a Tri-gate is proposed in this paper. The proposed power device consists of a triple RESURF drift region and a 3-D Tri-gate to achieve both lower drift region resistance and channel resistance. The simulation results show that the proposed power device has a specific on-resistance ( Ron,sp) of 9.85 mΩ.cm
²
and a figure of merit (FOM) of 4.069, which are reduced by more than 23% and improved by more than 30% in comparison to those of the conventional triple RESURF LDMOS power device at the same 200V breakdown voltage and 2.5 μ m channel length, respectively.