Low Power High Speed 15-Transistor Static True Single Phase Flip Flop

In any digital circuit design, Flip Flops are the most common and important building block. The factors affecting the design are the area, power and performance. The 3 parameters must be optimized for an efficient design. The focus is on the power and performance optimization in a time constrained design. There are many techniques to optimize PPA (Power Performance Area) factors. In this paper high speed low power 15-Transistor FF is proposed. The FF is designed in Master-Slave configuration. It is designed using static CMOS and complementary pass transistors logic. The FF is designed avoiding floating internal nodes to reduce dynamic power consumption. The Cadence Virtuoso tool is used for the implementation of the Flip Flop with supply voltage V
_DD
of 1V and clock frequency of 500MHz. The implementation technology used is 45nm. The results of the power dissipation and the delay is compared with Transmission Gate Flip Flops(TGFF), Topologically compressed Flip Flop(TCFF) and Logical structure Reduction Flip Flop (LRFF). Results of the proposed design was found that it is more efficient than the other compared FF designs. In comparison with TCFF, the PDP improvement of the proposed design was 49.298 at 10% switching factor.