Impact of Hot Carrier Degradation on GIDL Current in 45nm SOI-NFETs

The impact of hot-carrier stress on the device performance parameters such as ON-current, threshold voltage and transconductance has been studied extensively in the literature. However, limited work highlighting the impact on OFF-state performance is available. The ever increasing need for device scaling has resulted in severe implications of HCD on stress-induced drain leakage current as well. Therefore, in this work we have investigated through the experiments, the impact of DC stress on Gate-Induced-Drain-Leakage (GIDL) current in 45nm n-channel SOI MOSFETs. The total leakage current in the accumulation region under hot-carrier stress is dominated by GIDL current, which strongly correlates with interface state generation as well as bulk-oxide trapping. At different gate and drain stress-bias combinations, we notice reduction in GIDL current, which may be indicative of increased hole trapping in the bulk of the gate dielectric. This work is intended towards an exclusive investigation of hot-carrier stress induced GIDL degradation mechanisms and compares the trends for different HC energy modes. Based on different energy modes of hot-carrier degradation, we propose presence of two competing mechanisms; negatively charged interface states that cause increase in GIDL current and hole injection into gate dielectric bulk defects that reduces the GIDL current.