Repetitive-avalanche-induced Electrical Degradation and Optimization for 1.2kV 4H-SiC MOSFETs

Repetitive avalanche stress results in the injection of hot holes into the gate oxide interface, which leads to the degradations of electrical parameters, attracting wide attentions on improving the avalanche reliability of SiC power MOSFETs. A high avalanche reliability structure with two additional step gate oxides is then proposed in this work. With the help of Silvaco TCAD simulations, the optimized width and thickness of the additional oxides are determined. When compared with the conventional device structure, it is found that the peaks of perpendicular electric field and impact ionization rate of the improved structure under avalanche status are respectively reduced by 10% and 51%. Meanwhile, the breakdown voltage and the on-state resistance of the device are almost unchanged. Therefore, the improved device structure can effectively suppress the degradations caused by avalanche stress.