Methodology for Congestion Reduction and Timing Closure During Placement

Congestion and timing problems are the main hindrance in backend VLSI flow. Due to changing technology, there arises a need for improved and adaptive techniques to fix congestion and DRC (design rule check) violations. This paper shows the ways to have a proper congestion reduction algorithm and design rule check (DRC) of any SOC. It mainly focuses on removing congestion, and different ways to tackle problem for SOC in checking whether the design and timing requirements have been met or not. It also explains a methodology which will minimize congestion despite of having timing and design constraints. Finally, comparative analysis is done at 65 nm and 28 nm shows that the proposed algorithm provides a significant improvement in reducing congestion by 82% and still maintaining the performance of SOC. The results were obtained on Cadence Encounter Digital Implementation (EDI).