Understanding CdTe Performance with Engineered Front and Back Interfaces

CdTe device performance was simulated as a function of band alignment at the emitter/absorber and absorber/back buffer layer to determine under what conditions devices are front and back interface limited. When the back buffer layer forms an electron reflector, devices are limited by four separate mechanisms. When there is no electron reflector, the role of the back buffer layer increases. In addition to the front and back interfaces, Shockley-Reed-Hall (SRH) recombination can also determine the device performance. We determine the voltage at which SRH recombination dominates device performance for a number of carrier lifetimes. Finally, we show that increasing the CdTe dopant density reduces but does not eliminate the role of the back interface. These results help us interpret the improvements of real-life measurements, and will allow us to develop better front and back interfaces to CdTe.