Test cost reduction through increase in multi-site testing with reduced scan-out pins

For present day ICs, the time taken to test an IC directly impacts its overall cost. Hardware techniques like DFT compression architectures address this issue by reducing the number of test cycles required per pattern. In addition to this, multi-site testing techniques enable multiple ICs to be tested in parallel, resulting in further test time reduction. The ability to perform multi-site testing depends on the number of scan pins required for test. Fewer scan IOs means more ICs can be probed together for a given number of pins on a probe card during production testing which translates to test time reduction. Previously, we had proposed an on-chip signature comparison architecture for MISR compression techniques to improve diagnosability of compressed patterns and in this paper, we enhance the process to perform 100% compression based DFT tests with only 1 scan out pin instead of the conventional architectures that need 16 to 64 scan outs. The improvements in multi-site testing have been analyzed and calculated to be at least 1.5 times better than the conventional approach, resulting in significant reduction of test and thus the IC cost. The other aspects like area overhead, impact on tester data volume and test coverage have also been discussed in detail.